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RT9624B ? ds9624b-04 october 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? single phase synchronous rectified buck mosfet driver features z drive two n-mosfets z shoot through protection z embedded bootstrap diode z support high switching frequency z fast output rising time z tri-state pwm input for output shutdown z small sop-8, sop-8 (exposed pad) and 8-lead wdfn packages z rohs compliant and halogen free applications z core voltage supplies for desktop, motherboard cpu z high frequency low profile dc/dc converters z high current low voltage dc/dc converters z core voltage supplies for gfx card general description the RT9624B is a high frequency, synchronous rectified, single phase mosfet driver designed for normal mosfet driving applications and high performance cpu vr driving capabilities. the RT9624B can be supplied from 4.5v to 13.2v. the applicable power stage vin range is from 5v to 24v. the ic also builds in an internal power switch to replace external bootstrap diode. the RT9624B can support switching frequency efficiently up to 500khz. the ic has both the ugate and lgate driving circuits for synchronous rectified dc/dc converter applications. the shoot through protection mechanism is designed to prevent shoot through between high side and low side power mosfets. the RT9624B has tri-state pwm input with shutdown function, which can force driver to output low ugate and lgate signals. the RT9624B comes in a small footprint with 8-pin packages. the choice of package types includes sop-8, sop-8 (exposed pad) and wdfn-8l 3x3. vcc pwm gnd boot ugate phase lgate RT9624B 12v pwm controller c1 r1 q1 + v out q2 c boot c2 c3 r2 r3 r4 r5 l1 c4 c5 v in c6 simplified application circuit
RT9624B 2 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. (top view) sop-8 sop-8 (exposed pad) wdfn-8l 3x3 pin configurations boot pwm nc vcc ugate phase lgate gnd 2 3 4 5 6 7 8 boot pwm nc vcc ugate phase lgate gnd gnd 2 3 4 5 6 7 8 9 boot pwm vcc ugate phase gnd lgate nc 7 6 5 1 2 3 4 8 gnd 9 marking information 03 : product code ymdnn : date code RT9624Bzs : product number ymdnn : date code RT9624Bzsp : product number ymdnn : date code 03 ym dnn RT9624Bzqw RT9624Bzs RT9624Bzs RT9624B zsymdnn RT9624B zspymdnn lead plating system z : eco (ecological element with halogen free and pb free) RT9624B package type s : sop-8 sp : sop-8 (exposed pad-option1) qw : wdfn-8l 3x3 (w-type)
RT9624B 3 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram function pin description pin no. sop-8 sop-8 (exposed pad) / wdfn-8l 3x3 pin name pin function 1 1 boot bootstrap supply for high side gate drive. 2 2 pwm pwm signal input. connect this pin to the pwm output of the controller. 3 3 nc no internal connection. 4 4 vcc supply voltage input. 5 5 lgate low side gate driver output. connect this pin to the gate of low side power n-mosfet. 6 6, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 7 phase connect this pin to the source of the high side n-mosfet and the drain of the low side n-mosfet. 8 8 ugate high side gate drive output. connect this pin to the gate of high side power n-mosfet. shoot-through protection turn off detection shoot-through protection tri-state detect vcc pwm internal vdd boot ugate phase lgate gnd vcc por bootstrap control
RT9624B 4 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation por (power on reset) por block detects the voltage the vcc pin. when the vcc pin voltage is higher than por rising threshold, por block output is high. por output is low when vcc is not higher than por rising threshold. when the por block output is high, ugate and lgate can be controlled by pwm input voltage. if the por block output is low, both ugate and lgate will be pulled to low. tri-state detect when both por block output and en pin voltages are high, ugate and lgate can be controlled by pwm input. there are three pwm input modes, which are high, low, and shutdown state. if pwm input is within the shutdown window, both ugate and lgate output are low. when pwm input is higher than its rising threshold, ugate is high and lgate is low. when pwm input is lower than its falling threshold, ugate is low and lgate is high. bootstrap control bootstrap control block controls the integrated bootstrap switch. when lgate is high (low side mosfet is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to boot pin. when lgate is low (low side mosfet is turned off), the bootstrap switch is turned off to disconnect vcc pin and boot pin. turn-off detection turn-off detection block detects whether high side mosfet is turned off by monitoring phase pin voltage. to avoid shoot through between high side and low side mosfets, low side mosfet can be turned on only after high side mosfet is effectively turned off. shoot-through protection shoot-through protection block implements the dead time when both high side and low side mosfets are turned off. with shoot-through protection block, high side and low side mosfet are never turned on simultaneously. thus, shoot through between high side and low side mosfets is prevented.
RT9624B 5 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply voltage, vcc -------------------------------------------------------------------------------- ? 0.3v to 15v z boot to phase ------------------------------------------------------------------------------------- ? 0.3v to 15v z phase to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to 30v < 20ns --------------------------------------------------------------------------------------------------- ? 10v to 35v z lgate to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to (vcc + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- ? 2v to (vcc + 0.3v) z ugate to gnd dc -------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) z pwm to gnd ------------------------------------------------------------------------------------------ ? 0.3v to 7v z power dissipation, p d @ t a = 25 c sop-8 --------------------------------------------------------------------------------------------------- 0.833w sop-8 (exposed pad) ------------------------------------------------------------------------------ 1.333w wdfn-8l 3x3 ----------------------------------------------------------------------------------------- 1.429w z package thermal resistance (note 2) sop-8, ja --------------------------------------------------------------------------------------------- 120 c/w sop-8 (exposed pad), ja ------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc ------------------------------------------------------------------------ 15 c/w wdfn-8l 3x3, ja ------------------------------------------------------------------------------------ 70 c/w wdfn-8l 3x3, jc ------------------------------------------------------------------------------------ 8.2 c/w z lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c z junction temperature -------------------------------------------------------------------------------- 150 c z storage temperature range ----------------------- ------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) -------------------------------------- ----------------------------------- 2kv recommended operating conditions (note 4) z supply voltage, vcc -------------------------------------------------------------------------------- 4.5v to 13.2v z junction temperature range ----------------------- ------------------------------------------------ ? 40 c to 125 c z ambient temperature range ----------------------- ------------------------------------------------ ? 40 c to 85 c
RT9624B 6 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics parameter symbol test conditions min typ max unit power supply power supply voltage v cc 4.5 -- 13.2 v power supply current i vcc v boot = 12v, pwm input floating -- 120 -- a power on reset (por) por rising threshold v por_r v cc rising -- 4 4.4 v por falling threshold v por_ f v cc falling 3 3.5 -- v pwm input maximum input current i pwm pwm = 0v or 5v -- 160 -- a pwm floating voltage v pwm_fl pwm = open -- 1.8 -- v pwm rising threshold v pwm_rth 2.3 2.8 3.2 v pwm falling threshold v pwm_fth 0.7 1.1 1.4 v timing ugate rising time t ugater 3nf load -- 25 -- ns ugate falling time t ugatef 3nf load -- 12 -- ns lgate rising time t lgater 3nf load -- 24 -- ns lgate falling time t lgatef 3nf load -- 10 -- ns t ugatepdh -- 30 -- ugate propagation delay t ugatepdl v boot ? v phase = 12v see timing diagram -- 22 -- ns t lgatepdh see timing diagram -- 30 -- lgate propagation delay t lgatepdl see timing diagram -- 8 -- ns output ugate drive source r ugatesr v boot ? v phase = 12v, i source = 100ma -- 1.7 -- ugate drive sink r ugatesk v boot ? v phase = 12v, i sink = 100ma -- 1.4 -- lgate drive source r lgatesr i source = 100ma -- 1.6 -- lgate drive sink r lgatesk i sink = 100ma -- 1.1 -- (v cc = 12v, t a = 25 c unless otherwise specified)
RT9624B 7 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit timing diagram pwm ugate lgate t ugatepdh t lgatepdl t ugatepdl t lgatepdh 90% 90% 1.5v 1.5v 1.5v 1.5v vcc pwm gnd boot ugate phase lgate RT9624B q1 12v pwm controller + v out q2 c1 c boot c2 c3 c5 r1 r2 r3 r4 r5 l1 v in 2.2 1f 1 1f 2.2 0 1h 2.2 3.3nf 2200f x 2 c4 10f x 2 1000f x 3 c6 10f x 4 12v
RT9624B 8 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics time (20ns/div) dead time no load (5v/div) ugate phase lgate time (20ns/div) dead time no load (5v/div) ugate phase lgate time (20ns/div) pwm rising edge ugate (20v/div) phase (10v/div) pwm (10v/div) lgate (10v/div) time (20ns/div) pwm falling edge ugate (20v/div) phase (10v/div) pwm (10v/div) lgate (10v/div) time (20ns/div) dead time (5v/div) ugate phase lgate full load time (20ns/div) dead time (5v/div) full load ugate phase lgate
RT9624B 9 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (20ns/div) short pulse no load ugate phase lgate ugate ? phase (5v/div)
RT9624B 10 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT9624B is a high frequency, synchronous rectified, single phase dual mosfet driver containing richtek's advanced mosfet driver technologies. the RT9624B is designed to be able to adapt from normal mosfet driving applications to high performance cpu vr driving capabilities. supply voltage and power on reset the RT9624B can be utilized under both v cc = 5v or v cc = 12v applications which may happen in different fields of electronics application circuits. in terms of efficiency, higher v cc equals higher driving voltage of ugate/lgate which may result in higher switching loss and lower conduction loss of power mosfets. the choice of v cc = 12v or v cc = 5v can be a tradeoff to optimize system efficiency. the RT9624B is designed to drive both high side and low side n-mosfet through external input pwm control signal. it has power on protection function which held ugate and lgate low before the vcc voltage rises to higher than rising threshold voltage. tri-state pwm input after the initialization, the pwm signal takes the control. the rising pwm signal first forces the lgate signal to turn low then ugate signal is allowed to go high just after a non-overlapping time to avoid shoot through current. the falling of pwm signal first forces ugate to go low. when ugate and phase signal reach a predetermined low level, lgate signal is allowed to turn high. the pwm signal is acted as ? high? if the signal is above the rising threshold and acted as ? low? if the signal is below the falling threshold. when pwm signal level enters and remains within the shutdown window, the output drivers are disabled and both mosfet gates are pulled and held low. if the pwm signal is left floating, the pin will be kept around 1.8v by the internal divider and provide the pwm controller with a recognizable level. internal bootstrap power switch the RT9624B builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate pcb design and reduce total bom cost of the system. hence, no external bootstrap diode is required in real applications. non-overlap control to prevent the overlap of the gate drivers during the ugate pull low and the lgate pull high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to pull low (after propagation delay). before lgate is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1v. once the monitored voltages fall below 1.1v, lgate begins to turn high. by waiting for the voltages of the phase pin and high side gate driver to fall below 1.1v, the non-overlap protection circuit ensures that ugate is low before lgate pulls high. also to prevent the overlap of the gate drivers during lgate pull low and ugate pull high, the non-overlap circuit monitors the lgate voltage. when lgate goes below 1.1v, ugate goes high after propagation delay. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs1 or v gs2 is at 12v or 5v, the gate draws the current only for few nano-amperes. thus once the gate has been driven up to ? on? level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down 12v (or 5v) rapidly. it is also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows.
RT9624B 11 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 1. equivalent circuit and waveforms (v cc = 12v) in figure 1, the current i g1 and i g2 are required to move the gate up to 12v. the operation consists of charging c gd1 , c gd2 , c gs1 and c gs2 . c gs1 and c gs2 are the capacitors from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs1 and c gs2 are referred as ? c iss ? which are the input capacitors. c gd1 and c gd2 are the capacitors from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as ? c rss ? the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are shown as below : before driving the gate of the high side mosfet up to 12v, the low side mosfet has to be off; and the high side mosfet will be turned off before the low side is turned on. from figure 1, the body diode ? d 2 ? will be turned on before high side mosfets turn on. before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is gd1 gd1 gd1 r1 dv 12 i = c = c (3) dt t it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v gs1 = 12v, v gs2 = 12v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain from equation. (3) and (4) the total current required from the gate driving source can be calculated as the following equations. ( ) () =+= + = =+= += g1 gs1 gd1 g2 gs2 gd2 i i i 1.428 0.326 1.754 (a) (9) i i i 0.88 0.4 1.28 (a) (10) by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of the RT9624B. the v cb (the voltage difference between boot and phase on RT9624B) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c boot has to be selected properly. it is determined by the following constraints. g1 gs1 gs1 gs1 r1 g2 gs1 gs2 gs1 r2 dv c x 12 ic dt t dv c x 12 ic dt t == == (1) (2) -12 gs1 -9 -12 gs2 -9 1660 x 10 x 12 i 1.428 (a) 14 x 10 2200 x 10 x 12 i 0.88 (a) 30 x 10 == == (5) (6) () -12 gd1 -9 -12 gd2 -9 380 x 10 x 12 i 0.326 (a) 14 x 10 500 x 10 x 12+12 i 0.4 (a) 30 x 10 == == (7) (8) 12v t t v g2 v g1 v phase +12v l d 2 s 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 c gs1 c gd1 i gd1 i gs1 i g1 d 2 v out s 1 v in d 1 gnd g 1 v phase in gd2 gd2 gd2 r2 v12 dv i c c (4) dt t + ==
RT9624B 12 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 2. part of bootstrap circuit of RT9624B in practice, a low value capacitor c boot will lead to the over charging that could damage the ic. therefore, to minimize the risk of overcharging and to reduce the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low-esr capacitor should be used to provide good local de-coupling. it is recommended to adopt a ceramic or tantalum capacitor. power dissipation to prevent driving the ic beyond the maximum recommended operating junction temperature of 125 c, it is necessary to calculate the power dissipation appropriately. this dissipation is a function of switching frequency and total gate charge of the selected mosfet. figure 3 shows the power dissipation test circuit. c l and c u are the ugate and lgate load capacitors, respectively. the bootstrap capacitor value is 1 f. figure 3. power dissipation test circuit figure 4 shows the power dissipation of the RT9624B as a function of frequency and load capacitance when v cc = 12v . the value of c u and c l are the same and the frequency is varied from 100khz to 1mhz. the operating junction temperature can be calculated from the power dissipation curves (figure 4). assume v cc = 12v, operating frequency is 200khz and c u = c l = 1nf which emulate the input capacitances of the high side and low side power mosfets. from figure 4, the power dissipation is 100mw. thus, for example, with the sop- 8 package, the package thermal resistance ja is 120 c/ w. the operating junction temperature is then calculated as : t j = (120 c/w x 100mw) + 25 c = 37 c (11) where the ambient temperature is 25 c. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. figure 4. power dissipation vs. frequency v in c boot v cb + - boot v cc ugate phase lgate gnd vcc pwn gnd boot ugate phase lgate RT9624B 1f c l 3nf 20 2n7002 2n7002 12v 12v 1f pwm c boot 10 c u 3nf power dissipation vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 frequency (khz) power dissipation (mw) v cc = 12v c u = c l = 1nf c u = c l = 3nf c u = c l = 2nf
RT9624B 13 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout consideration figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9624B. the converter operates from 5v to 12v of input voltage. for the pcb layout , it should be very careful. the power circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the location of q1, q2, l1 should be very close. next, the trace from ugate, and lgate should also be short to decrease the noise of the driver output signals. phase signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c1 should be connected to gnd directly. furthermore, the bootstrap capacitors (c boot ) should always be placed as close to the pins of the ic as possible. figure 6. synchronous buck converter circuit figure 5. derating curve of maximum power dissipation for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 package, the thermal resistance, ja , is 120 c/w on a standard jedec 51-7 four-layer thermal test board. for sop-8 (exposed pad) package, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-8l 3x3 package, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for sop-8 package p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-8l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. boot ugate phase lgate vcc RT9624B gnd c boot 12v l2 c3 v in v core c6 phb83n03lt phb95n03lt l1 q2 q1 c5 + + 12v pwm pwm c1 r1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0255075100125 ambient temperature (c) maximum power dissipation (w ) wdfn-8l 3x3 four-layer pcb sop-8 (exposed pad) sop-8
RT9624B 14 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
RT9624B 15 ds9624b-04 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138
RT9624B 16 ds9624b-04 october 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 2.950 3.050 0.116 0.120 d2 2.100 2.350 0.083 0.093 e 2.950 3.050 0.116 0.120 e2 1.350 1.600 0.053 0.063 e 0.650 0.026 l 0.425 0.525 0.017 0.021 w-type 8l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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